(1) Field of the Invention
This invention relates to an improved non-volatile memory (NVM) structure and a method for integrating several memory devices into a single monolithic memory. More particularly this invention relates to forming concurrently an array of devices that includes a NOR-type flash memory device, a NAND-type flash memory device, and a three-transistor EEPROM device on a single substrate with programming/erase voltages that are more compatible over the prior art.
(2) Description of the Prior Art
Non-volatile memory (NVM) flash memory formed from arrays of EEPROM transistors are finding increasing applications in smart cards for recording, storing and transporting digital information. For example, flash memory cards are currently used in digital cameras for recording and storing pictures that can be later displayed on personal computers (PCs), TVs or printed. Flash memories in smart cards are being used not only for storing data but also for storing application programs and the like. These smart cards are finding increasing use in applications such as fingerprint identification, identification cards, health records, transportation programs and many more applications which include encryption for personal security, and also applications such as e-passport, credit card, JAVA card subscriber identity module (SIM).
Basically the non-volatile memory in these smart cards consists of Electrically Erasable Programmable Read Only Memory (EEPROM) transistors configured into an array of EEPROMs to form NOR and NAND flash memory which can be programmed and erased to store data (information) and application programs and the like, and are accessed through peripheral circuits that are also integrated onto the same semiconductor chip.
These EEPROMs are similar to conventional field effect transistors (FETs) but with an additional floating gate (FG). The FG is formed on a thin gate oxide between the control gate (CG) and the FET channel which is between the FET source and drain areas on a semiconductor substrate. The floating gate (FG) is electrically isolated and can be charged by generating an electric field by applying an electric potential between the control gate (CG) and substrate. Electrons are injected either by hot electron injection (HEI) or by Fowler-Nordheim (FN) tunneling through the thin gate oxide to charge or discharge the FG. This charged state remains on the FG after the power source is removed because the FG is electrically isolated (insulated) which results in non-volatile memory (NVM).
By using appropriate sensing circuits one can determine whether the EEPROM floating gate (FG) is charged or not. By sensing the state of the EEPROM one can utilize the charge state to represent binary 0 and 1. Arrays of EEPROMs can be used to store application programs and large amounts of data in binary form for information purposes, and can include other circuits that carry out Boolean algebra (logic).
In today's NVM technologies the two most commonly used memory circuits are the NOR-type flash memory and the NAND-type flash memory. In the NOR-type memory the individual EEPROM transistors are connected in parallel. FIG. 31 shows a schematic of a portion of a NOR circuit. In FIG. 31 the EEPROM transistors Tx1, Tx2, and Tx3 are connected in parallel between a bit line (FET drain) and a sense line (FET source). Arrays of NOR memory cells are faster for read/write (program/erase) than the conventional NAND memory cells. NOR cells require higher power but are much larger and require greater area per unit memory cell on the substrate. Arrays of NOR cells (NOR-flash memory) are preferred for programming applications, but are not desirable for mass storage of data.
In the NAND-type memory the individual floating-gate transistors are connected in series. One arrangement is shown in the schematic in FIG. 30 for a 16-bit series of NAND cells. As shown in FIG. 30 the floating-gate transistors (cells) are connected in series with conventional (single-gate) FETs SG1 and SG2 for selecting (accessing) the series of NAND memory cells for programming or erasing data. A bit line (BL) and word lines (WL) 1–16 are also shown for a portion of a NAND memory array. This array of NAND memory cells has slower read times than the NOR-type memory, but the NAND circuit consumes much less power and has much higher cell density than the NOR-type memory. Therefore NAND memory is preferred for mass storage of data, in which the data requires frequent updates. Likewise NOR memory is more desirable for storing CPU and application programs and the like, since programs require infrequent updating. Also the program/erase (P/E) cycle for the NOR circuit is shorter than the P/E cycle for the NAND.
Another memory device that is desirable on the smart card is a 3-transistor EEPROM cell array used for storing a few bytes of information that is changed frequently. A single 3-transistor EEPROM cell is shown in FIG. 31. The 3-transistor EEPROM cell consists of a floating-gate transistor between and in series with two select transistors labeled STX1 and STX2. Arrays of these 3-transistor EEPROM cells are desirable for storing small groups of bytes of information that are frequently updated.
As applications of the smart cards become more diverse, it is highly desirable to integrate all three memory types on a single P-substrate (chip) for superior erase and program operation in units of bytes and pages as opposed to Toshiba's approach.
Numerous methods for making programmable nonvolatile memory have been reported in the literature. For example, one method for making non-volatile semiconductor memory is described in U.S. Pat. No. 6,801,458 B2 to Sakui et al. in which 3-transistor memory cell arrays are merged with NAND-type memory. Each 3-transistor cell is an EEPROM transistor sandwiched between two select transistors. However, Sakui does not merge a NOR-type memory with a NAND-type memory because Sakui cannot generate a negative high voltage such as −18 V on a triple-well process which allows the erase and program functions more efficiently performed in units of bytes and pages for the NOR-type circuits as well as NAND-type Flash and 3-T or 4-T EEPROM without a big waste in well spacing of three-cell arrays.
However, there is no prior art that appears to satisfy the requirement for making compatible NOR, NAND and 3-transistor EEPROMs on the same chip. Therefore, there is still a strong need in the semiconductor industry for making flash memory for a smart card, embedded flash and many others using a single compatible (unified) semiconductor process for making NOR, NAND and 3-transistor EEPROMs on the same chip.